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Optical phase-change materials have enabled nonvolatile programmability in integrated photonic circuits by leveraging a reversible phase transition between amorphous and crystalline states. To control these materials in a scalable manner on-chip, heating the waveguide itself via electrical currents is an attractive option which has been recently explored using various approaches. Here, we compare the heating efficiency, fabrication variability, and endurance of two promising heater designs which can be easily integrated into silicon waveguides—a resistive microheater using n-doped silicon and one using a silicon p-type/intrinsic/n-type (PIN) junction. Raman thermometry is used to characterize the heating efficiencies of these microheaters, showing that both devices can achieve similar peak temperatures but revealing damage in the PIN devices. Subsequent endurance testing and characterization of both device types provide further insights into the reliability and potential damage mechanisms that can arise in electrically programmable phase-change photonic devices. 

Phase change chalcogenides such as Ge₂Sb₂Te₅(GST) have recently enabled advanced optical devices for applications such as in-memory computing, reflective displays, tunable metasurfaces, and reconfigurable photonics. However, designing phase change optical devices with reliable and efficient electrical control is challenging due to the requirements of both high amorphization temperatures and extremely fast quenching rates for reversible switching. Here, we use a Multiphysics simulation framework to model three waveguide-integrated microheaters designed to switch optical phase change materials. We explore the effects of geometry, doping, and electrical pulse parameters to optimize the switching speed and minimize energy consumption in these optical devices. 

Neuromorphic computing has recently emerged as a promising paradigm to overcome the von-Neumann bottleneck and enable orders of magnitude improvement in bandwidth and energy efficiency. However, existing complementary metal-oxide-semiconductor (CMOS) digital devices, the building block of our computing system, are fundamentally different from the analog synapses, the building block of the biological neural network—rendering the hardware implementation of the artificial neural networks (ANNs) not scalable in terms of area and power, with existing CMOS devices. In addition, the spatiotemporal dynamic, a crucial component for cognitive functions in the neural network, has been difficult to replicate with CMOS devices. Here, we present the first topological insulator (TI) based electrochemical synapse with programmable spatiotemporal dynamics, where long-term and short-term plasticity in the TI synapse are achieved through the charge transfer doping and ionic gating effects, respectively. We also demonstrate basic neuronal functions such as potentiation/depression and paired-pulse facilitation with high precision (>500 states per device), as well as a linear and symmetric weight update. We envision that the dynamic TI synapse, which shows promising scaling potential in terms of energy and speed, can lead to the hardware acceleration of truly neurorealistic ANNs with superior cognitive capabilities and excellent energy efficiency. 

Neuromorphic computing has the great potential to enable faster and more energy‐efficient computing by overcoming the von Neumann bottleneck. However, most emerging nonvolatile memory (NVM)‐based artificial synapses suffer from insufficient precision, nonlinear synaptic weight update, high write voltage, and high switching latency. Moreover, the spatiotemporal dynamics, an important temporal component for cognitive computing in spiking neural networks (SNNs), are hard to generate with existing complementary metal–oxide–semiconductor (CMOS) devices or emerging NVM. Herein, a three‐terminal, Li_xWO₃‐based electrochemical synapse (LiWES) is developed with low programming voltage (0.2 V), fast programming speed (500 ns), and high precision (1024 states) that is ideal for artificial neural networks applications. Time‐dependent synaptic functions such as paired‐pulse facilitation (PPF) and temporal filtering that are critical for SNNs are also demonstrated. In addition, by leveraging the spike‐encoded timing information extracted from the short‐term plasticity (STP) behavior in the LiWES, an SNNs model is built to benchmark the pattern classification performance of the LiWES, and the result indicates a large boost in classification performance (up to 128×), compared with those NO‐STP synapses.